1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a semiconductor device having a data line for transmitting data which is output from a memory cell array.
2. Description of the Background Art
In accordance with increase in density and integration of semiconductor memory devices, a data line pair for transmitting data which is read out from a memory cell array is increased in length and density. Furthermore, a data line pair tends to have more capacity than before, resulting in longer equalizing time of the data line pair. However, it is necessary to reduce the equalizing time and to read out data at a high speed for fast operation of semiconductor memory devices.
Now, a conventional semiconductor memory device will be described with reference to the drawings. FIG. 10 is a block diagram showing a structure of a DRAM (Dynamic Random Access Memory), conventional semiconductor memory device.
Referring to FIG. 10, the semiconductor memory device includes a control circuit 101, a row address buffer 102, a column address buffer 103, a row decoder 104, a memory cell array 105, a sense amplifier portion 106, a column switch 107, a column decoder 108, an equalizing circuit 110, a preamplifier 112, a main amplifier 113, a writing circuit 114, and a data buffer 115.
Control circuit 101 receives such external control signals as a row address strobe signal/RAS ("/" indicates an inverted signal), a column address strobe signal /CAS and a write enable signal /WE, and outputs a prescribed control signal to internal blocks. Row address buffer 102 receives an external row address signal RA and outputs an internal row address signal to row decoder 104. Column address buffer 103 receives an external column address signal CA and outputs an internal column address signal to column decoder 108. Column address buffer 103 activates column decoder 108 and outputs to column decoder 108 a column control signal A changing in response to column address signal CA.
Memory cell array 105 includes a plurality of word lines connected to the row decoder, a plurality of bit line pairs arranged crossing the word lines, and a plurality of memory cells arranged at the intersections of the word lines and the bit line pairs. Row decoder 104 activates a prescribed word line in response to the internal row address signal. Column decoder 108 turns on column switch 107 in response to the internal column address signal and connects the selected bit line pair and a data input/output line pair IO. Data of the selected memory cell is transmitted through the bit line pair, amplified at sense amplifier portion 106, and is output to data input/output line pair IO through column switch 107.
Equalizing circuit 110 equalizes and precharges data input/output line pair IO before data is read out to data input/output line pair IO. Data which is read out to the equalized data input/output line pair IO is input to preamplifier 112. Preamplifier 112 amplifies the signal transmitted through data input/output line pair IO in response to a preamplifier enable signal PAE, and outputs the amplified signal to main amplifier 113 as a read data signal RD. Main amplifier 113 amplifies read data signal RD in response to an output enable signal OEM, and outputs the amplified signal as an output data Q.
In writing operation, an input data Din is input externally to data buffer 115, which latches input data Din in response to a data in latch signal DIL and outputs the data to writing circuit 114. Writing circuit 114 transmits the input data to data input/output line pair IO in response to a write data enable signal WDE. The data transmitted to data input/output line pair IO is sent through column switch 107 to a prescribed bit line pair and data is written in a prescribed memory cell.
Next, the column switch shown in FIG. 10 will be described in detail. FIG. 11 shows a specific structure of the column switch shown in FIG. 10.
Referring to FIG. 11, column switch 107 includes NMOS transistors Q91-Q94. Equalizing circuit 110 includes NMOS transistors Q95-Q97. Memory cell array 105 includes a word line WL, bit line pairs BL0, /BL0 and BL1, /BL1 ("/" indicates a complementary signal line) and a memory cell MC. Only two bit lines are shown in FIG. 11 for illustrative purpose.
A plurality of word lines WL are connected to row decoder 104, which activates a prescribed word line WL in response to the input internal row address signal.
A plurality of bit line pairs BL0, /BL0 and BL1, /BL1 are arranged to cross the plurality of word lines WL, and a memory cell MC is disposed at each intersection. When word line WL is activated, data stored in memory cell MC is read out to the corresponding bit line pair. The plurality of bit line pairs BL0, /BL0 and BL1, /BL1 are connected to sense amplifiers (SA) 106a and 106b, respectively. Data of the bit line pair corresponding to the activated word line WL is amplified by the sense amplifier.
Transistor Q91 is connected to bit line BL0 and data input/output line IO. Transistor Q92 is connected to bit line /BL0 and data input/output line /IO. Transistors Q91 and Q92 receive at their gates a column selection signal CSL0 which is output from column decoder 108. Transistors Q93 and Q94 make a similar connection and operate in a similar manner. In order to connect a prescribed bit line pair and the data input/output line pair based on the input internal column address signal and column control signal A, column decoder 108 raises the column selection signal from "L" (Low) to "H" (High), turns on the corresponding transistor, and connects the bit line pair and the data input/output line pair. As a result, the data amplified by the sense amplifier is transmitted to data input/output line pair IO, /IO through column switch 107.
Data input/output line pair IO, /IO is connected to equalizing circuit 110. Transistor Q95 equalizes data input/output line pair IO, /IO in response to an equalizing signal EQ. Transistors Q96 and Q97 precharge data input/output line pair IO, /IO at a prescribed precharge voltage V.sub.BL in response to equalizing signal EQ. After data input/output line pair IO, /IO is equalized and precharged by equalizing circuit 110, data amplified by the sense amplifier is read out to data input/output line pair IO, /IO, and then is input to preamplifier 112. Preamplifier 112 further amplifies the input data, and outputs the resulting data to main amplifier 113 as read data signal RD.
Next, operation of the above column switch will be described in detail. FIGS. 12(a) to 12(e) are timing charts illustrating operation of the column switch shown in FIG. 11.
FIGS. 12(a) to 12(e) show an example where bit line pair BL0, /BL0 is selected first and then bit line pair BL1, /BL1 is selected. When column control signal A rises from "L" to "H", column control signal CSL0 rises to "H". As a result, transistors Q91 and Q92 turn on, and data of bit line pair BL0, /BL0 is read out to data input/output line pair IO, /IO.
When column control signal A falls from "H" to "L" after a prescribed time period, column control signal CSL0 falls from "H" to "L". Consequently, transistors Q91 and Q92 turn off, and data transmission from bit line pair BL0, /BL0 to data input/output line pair IO, /IO is terminated. When column control signal A falls from "H" to "L", equalizing signal EQ rises from "L" to "H". With the rise of equalizing signal EQ, transistors Q95, Q96 and Q97 turn on, and data input/output line pair IO, /IO is equalized and precharged at a prescribed potential.
Next, when column control signal A rises from "L" to "H", column control signal CSL1 rises from "L" to "H", transistors Q93 and Q94 turn on, and bit line pair BL1, /BL1 and data input/output line pair IO, /IO are connected. As a result, data of bit line pair BL1, /BL1 is read out to data input/output line pair IO, /IO.
When column control signal A rises from "L" to "H", equalizing signal EQ falls from "H" to "L", and transistors Q95, Q96 and Q97 turn off, thereby terminating equalizing and precharging operation.
As described above, equalizing and precharging operation has been carried out for a prescribed time period whenever data is read out from a prescribed bit line pair to data input/output line pair IO, /IO.
Operation of a conventional semiconductor memory device utilizing the column switch above will now be described in detail. FIGS. 13(a) to 13(j) are timing charts illustrating operation of the semiconductor memory device shown in FIG. 10.
Referring to FIGS. 13(a) to 13(j), the externally applied row address strobe signal /RAS falls to "L" and an externally applied row address signal R1 is read. Row decoder 104 activates word line WL corresponding to row address signal R1.
Next, the externally applied column address strobe signal /CAS falls from "H" to "L" and an externally applied column address signal C1 is read. Column decoder 108 raises column control signal CSL0 from "L" to "H" in order to connect data input/output line pair IO, /IO and bit line pair BL0, /BL0 corresponding to column address signal C1. Transistors Q91 and Q92 turn on in response to column control signal CSL0 and data is read to data input/output line pair IO, /IO. Preamplifier 112 amplifies the data read out to data input/output line pair IO, /IO in response to preamplifier enable signal PAE and outputs the amplified data to main amplifier 113 as read data signal RD. Main amplifier 113 further amplifies the input read data signal RD in response to output enable signal OEM and outputs the resultant data as output data Q.
After a prescribed time period, when column address strobe signal /CAS rises from "L" to "H", column control signal CSL0 falls from "H" to "L", terminating readout of data. At this time, preamplifier enable signal PAE and output enable signal OEM also fall from "H" to "L", and output of data from preamplifier 112 and main amplifier 113 is terminated.
For a time T, data input/output line pair IO, /IO is equalized and precharged by equalizing circuit 110 so as to read out next data.
After time T has passed, column address strobe signal /CAS falls from "H" to "L" and column address signal C2 is read. Data readout continues in a similar manner, and data which is read out from bit line pair BL1, /BL1 is transmitted to data input/output line pair IO, /IO, amplified by and output as output data Q from main amplifier 113.
As described above, in a conventional semiconductor memory device, equalizing time T has been required before data which is read out from the bit line pair is transmitted to data input/output line pair IO, /IO. Equalizing time T requires, for example, at least 10 ns even in the fast page mode, giving rise to a problem that data readout cannot be achieved at high speed.
When equalizing time T is reduced, it takes time to invert data of data input/output line pair IO, /IO because the input/output line pair cannot be fully equalized. Therefore, this approach cannot achieve high-speed data readout, either.